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ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
16 years 23 days ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
RSP
2006
IEEE
116views Control Systems» more  RSP 2006»
16 years 8 days ago
Performance Evaluation of an Adaptive FPGA for Network Applications
This paper presents the design and the performance evaluation of a coarse-grain dynamically reconfigurable platform for network applications. The platform consists of two MicroBla...
Christoforos Kachris, Stamatis Vassiliadis
ICPP
1996
IEEE
15 years 10 months ago
Scheduling of Wavefront Parallelism on Scalable Shared-memory Multiprocessors
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
Naraig Manjikian, Tarek S. Abdelrahman
DAC
2001
ACM
16 years 7 months ago
Dynamic Voltage Scaling and Power Management for Portable Systems
Portable systems require long battery lifetime while still delivering high performance. Dynamic voltage scaling (DVS) algorithms reduce energy consumption by changing processor sp...
Tajana Simunic, Luca Benini, Andrea Acquaviva, Pet...
DAC
2005
ACM
16 years 7 months ago
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology
In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...