1834 search results - page 211 / 367 » A Dynamic Multithreading Processor |
133
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RTSS
1999
IEEE
15 years 9 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
133
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ISCA
1998
IEEE
15 years 9 months ago
1998
IEEE
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors that execute instructions speculatively. Some of the best current predic...
150
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ICPP
1993
IEEE
15 years 9 months ago
1993
IEEE
SIMD or vector computers and collection-oriented languages, like C , are designed to perform the same computation on each data item or on just a subset of the data. Subsets of pro...
136
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DAC
2005
ACM
15 years 7 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
135
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JILP
2000
15 years 4 months ago
2000
Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instructio...