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» A Dynamic Multithreading Processor
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98
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ICCAD
2002
IEEE
157views Hardware» more  ICCAD 2002»
15 years 9 months ago
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
Steven M. Martin, Krisztián Flautner, Trevo...
110
Voted
SCAM
2005
IEEE
15 years 6 months ago
A Fast Analysis for Thread-Local Garbage Collection with Dynamic Class Loading
Long-running, heavily multi-threaded, Java server applications make stringent demands of garbage collector (GC) performance. Synchronisation of all application threads before garb...
Richard E. Jones, Andy C. King
ISCA
1997
IEEE
103views Hardware» more  ISCA 1997»
15 years 4 months ago
Designing High Bandwidth On-Chip Caches
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
Kenneth M. Wilson, Kunle Olukotun
82
Voted
ENTCS
2007
91views more  ENTCS 2007»
15 years 18 days ago
Dynamic Reverse Code Generation for Backward Execution
The need for backward execution in debuggers has been raised a number of times. Backward execution helps a user naturally think backwards and, in turn, easily locate the cause of ...
Jooyong Lee
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
15 years 9 months ago
Speculative Trace Scheduling in VLIW Processors
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...
Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhov...