Sciweavers

746 search results - page 147 / 150
» A Dynamic Platform for Runtime Adaptation
Sort
View
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 1 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
IPPS
1999
IEEE
15 years 1 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
14 years 11 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
OSDI
1996
ACM
14 years 10 months ago
Automatic Compiler-Inserted I/O Prefetching for Out-of-Core Applications
Current operating systems offer poor performance when a numeric application's working set does not fit in main memory. As a result, programmers who wish to solve "out-of...
Todd C. Mowry, Angela K. Demke, Orran Krieger
CGF
2002
149views more  CGF 2002»
14 years 9 months ago
Using Perceptual Texture Masking for Efficient Image Synthesis
Texture mapping has become indispensable in image synthesis as an inexpensive source of rich visual detail. Less obvious, but just as useful, is its ability to mask image errors d...
Bruce Walter, Sumanta N. Pattanaik, Donald P. Gree...