68 search results - page 10 / 14 » A Family of Logical Fault Models for Reversible Circuits |
105
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DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diagnosis. In contrast to previous approaches which identify candidates by utilizin...
CL
2000
Springer
15 years 4 months ago
2000
Springer
A number of diagnostic and optimisation problems in Electronics Computer Aided Design have usually been handled either by specific tools or by mapping them into a general problem s...
JUCS
2007
14 years 11 months ago
2007
: This paper describes a method of using Petri net P-invariants in system diagnosis. To model this process a net oriented fault classification is presented. Hence, the considered d...
110
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VTS
2002
IEEE
15 years 4 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
111
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EVOW
2001
Springer
15 years 4 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...