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» A Fast FPGA Implementation of a General Purpose Neuron
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DATE
2008
IEEE
99views Hardware» more  DATE 2008»
15 years 4 months ago
GMDS: Hardware implementation of novel real output queuing architecture
In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose lin...
R. Arteaga, Félix Tobajas, Roberto Esper-Ch...
FPL
1995
Springer
137views Hardware» more  FPL 1995»
15 years 1 months ago
High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform
General purpose custom computing platforms, such as Splash-2, have demonstrated the ability to enter mainstream computing not only due to their near application-specific speeds bu...
Ramana V. Rachakonda, Peter M. Athanas, A. Lynn Ab...
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
15 years 2 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
63
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FPL
1999
Springer
95views Hardware» more  FPL 1999»
15 years 1 months ago
FPGA Viruses
Programmable logic is widely used, for applications ranging from eld-upgradable subsystems to advanced uses such as recon gurable computing platforms which are modi able at run-tim...
Ilija Hadzic, Sanjay Udani, Jonathan M. Smith
FPGA
2000
ACM
120views FPGA» more  FPGA 2000»
15 years 1 months ago
A novel high throughput reconfigurable FPGA architecture
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, M...