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ICML
2006
IEEE
16 years 1 months ago
Maximum margin planning
Mobile robots often rely upon systems that render sensor data and perceptual features into costs that can be used in a planner. The behavior that a designer wishes the planner to ...
Nathan D. Ratliff, J. Andrew Bagnell, Martin Zinke...
ISBI
2004
IEEE
16 years 1 months ago
Cortical Surface Flattening Using Least Square Conformal Mapping with Minimal Metric Distortion
Although flattening a cortical surface necessarily introduces metric distortion due to the non-constant Gaussian curvature of the surface, the Riemann Mapping Theorem states that ...
Lili Ju, Josh Stern, Kelly Rehm, Kirt Schaper, Dav...
VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
16 years 1 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
VLSID
2002
IEEE
105views VLSI» more  VLSID 2002»
16 years 1 months ago
A Heuristic for Clock Selection in High-Level Synthesis
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
DCC
2007
IEEE
16 years 22 days ago
Efficient pairing computation on supersingular Abelian varieties
Abstract. We present a general technique for the efficient computation of pairings on supersingular Abelian varieties. This formulation, which we call the eta pairing, generalises ...
Paulo S. L. M. Barreto, Steven D. Galbraith, Colm ...