36 search results - page 2 / 8 » A Fast Two-level Logic Minimizer |
DAC
2002
ACM
14 years 7 months ago
2002
ACM
VLSID
1998
IEEE
13 years 10 months ago
1998
IEEE
ASPDAC
2005
ACM
13 years 8 months ago
2005
ACM
- We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory p...
DDECS
2008
IEEE
14 years 21 days ago
2008
IEEE
: We propose a simple and fast two-level minimization algorithm for completely specified functions in this paper. The algorithm is based on processing ternary trees. A ternary tree...
TMC
2012
11 years 8 months ago
2012
—We investigate the following fundamental question—how fast can information be collected from a wireless sensor network organized as tree? To address this, we explore and evalu...