79 search results - page 15 / 16 » A Formal Automated Approach for Reverse Engineering Programs... |
VMCAI
2005
Springer
13 years 11 months ago
2005
Springer
When a system fails to satisfy its specification, the model checker produces an error trace (or counter-example) that demonstrates an undesirable behavior, which is then used in d...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
SEW
2003
IEEE
13 years 11 months ago
2003
IEEE
Runtime monitoring is aimed at ensuring correct runtime behavior with respect to specified constraints. It provides assurance that properties are maintained during a given program...
ICSE
2008
IEEE-ACM
14 years 7 months ago
2008
IEEE-ACM
Timed Interval Calculus (TIC) is a highly expressive set-based notation for specifying and reasoning about embedded real-time systems. However, it lacks mechanical proving support...
SIGSOFT
2007
ACM
14 years 7 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...