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» A Formal Verification Approach for IP-based Designs
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2000
IEEE
15 years 6 months ago
Model Checking of Workflow Schemas
Practical experience indicates that the definition of realworld workflow applications is a complex and error-prone process. Existing workflow management systems provide the means,...
Christos T. Karamanolis, Dimitra Giannakopoulou, J...
SIGSOFT
2010
ACM
14 years 11 months ago
Software economies
Software construction has typically drawn on engineering metaphors like building bridges or cathedrals, which emphasize architecture, specification, central planning, and determin...
David F. Bacon, Eric Bokelberg, Yiling Chen, Ian A...
136
Voted
CODES
2008
IEEE
15 years 3 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
129
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WWW
2005
ACM
16 years 2 months ago
Consistency checking of UML model diagrams using the XML semantics approach
A software design is often modeled as a collection of unified Modeling Language (UML) diagrams. There are different aspects of the software system that are covered by many differe...
Yasser Kotb, Takuya Katayama
DAC
2003
ACM
16 years 2 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...