154 search results - page 18 / 31 » A Formal Verification Approach for IP-based Designs |
126
Voted
VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
DAC
2003
ACM
16 years 2 months ago
2003
ACM
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
124
Voted
VLSID
2001
IEEE
16 years 2 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
123
Voted
GLVLSI
2008
IEEE
15 years 2 months ago
2008
IEEE
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
120
Voted
INFORMATICALT
2002
15 years 1 months ago
2002
This paper is concerned with design, implementation and verification of persistent purely functional data structures which are motivated by the representation of natural numbers us...