154 search results - page 20 / 31 » A Formal Verification Approach for IP-based Designs |
152
Voted
DAC
2010
ACM
15 years 5 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
107
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SIMUTOOLS
2008
15 years 3 months ago
2008
Model checking is a suitable formal technique to analyze parallel programs' execution in an industrial context because automated tools can be designed and operated with very ...
133
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FOSSACS
2008
Springer
15 years 3 months ago
2008
Springer
Whereas formal verification of timed systems has become a very active field of research, the idealised mathematical semantics of timed automata cannot be faithfully implemented. Se...
117
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FM
2008
Springer
15 years 3 months ago
2008
Springer
TLM (Transaction-Level Modeling) was introduced to cope with the increasing complexity of Systems-on-Chip designs by raising the modeling level. Currently, TLM is primarily used fo...
111
Voted
DAC
2007
ACM
15 years 5 months ago
2007
ACM
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...