154 search results - page 23 / 31 » A Formal Verification Approach for IP-based Designs |
104
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DATE
2000
IEEE
15 years 6 months ago
2000
IEEE
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
109
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BCS
2008
15 years 3 months ago
2008
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
129
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DAC
2007
ACM
15 years 5 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
133
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ICCAD
2007
IEEE
15 years 10 months ago
2007
IEEE
Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, …, gn}, i.e. f = h(g1, …, gn). It plays an important r...
108
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TSMC
2010
14 years 8 months ago
2010
Computer system reliability is conventionally modeled and analyzed using techniques such as fault tree analysis (FTA) and reliability block diagrams (RBD), which provide static rep...