154 search results - page 26 / 31 » A Formal Verification Approach for IP-based Designs |
107
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VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
144
Voted
GLVLSI
2007
IEEE
15 years 5 months ago
2007
IEEE
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
238
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CASES
2011
ACM
14 years 1 months ago
2011
ACM
This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarc...
111
Voted
EMSOFT
2010
Springer
14 years 11 months ago
2010
Springer
SystemC is the de facto standard for modeling embedded systems. It allows system design at various levels of abstractions, provides typical object-orientation features and incorpo...
191
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B
2007
Springer
15 years 5 months ago
2007
Springer
Abstract. A recent contribution to the formal specification and verification of concurrent systems is the integration of the state- and event-based approaches B and CSP, specifical...