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SAS
2009
Springer
281views Formal Methods» more  SAS 2009»
16 years 9 days ago
A Verifiable, Control Flow Aware Constraint Analyzer for Bounds Check Elimination
The Java programming language requires that out-of-bounds array accesses produce runtime exceptions. In general, this requires a dynamic bounds check each time an array element is...
David Niedzielski, Jeffery von Ronne, Andreas Gamp...
FMCAD
2008
Springer
15 years 1 months ago
Automatic Non-Interference Lemmas for Parameterized Model Checking
Parameterized model checking refers to any method that extends traditional, finite-state model checking to handle systems arbitrary number of processes. One popular approach to thi...
Jesse D. Bingham
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 11 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
KBSE
1998
IEEE
15 years 4 months ago
Planning Equational Verification in CCS
Most efforts to automate formal verification of communicating systems have centred around finite-state systems (FSSs). However, FSSs are incapable of modelling many practical comm...
Raul Monroy, Alan Bundy, Ian Green
BCSHCI
2007
15 years 1 months ago
Using formal models to design user interfaces: a case study
The use of formal models for user interface design can provide a number of benefits. It can help to ensure consistency across designs for multiple platforms, prove properties such...
Judy Bowen, Steve Reeves