496 search results - page 94 / 100 » A Framework for Analyzing Parallel Simulation Performance |
105
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HPCA
2012
IEEE
13 years 5 months ago
2012
IEEE
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
92
Voted
EAAI
2006
14 years 9 months ago
2006
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI ...
110
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GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
ISCA
2007
IEEE
15 years 4 months ago
2007
IEEE
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
ICC
2007
IEEE
15 years 4 months ago
2007
IEEE
—An adaptive multiple input and multiple output with the code matrix index feedback [8]. One detector will (MIMO) system based on the unified belief propagation (BP) work in the ...