1420 search results - page 13 / 284 » A Framework for Scheduler Synthesis |
ATVA
2009
Springer
15 years 3 months ago
2009
Springer
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
EUROPAR
2006
Springer
15 years 3 months ago
2006
Springer
This paper presents the integration of a multi-level scheduler in the YML architecture. It demonstrates the advantages of this architecture based on a component model and why it is...
109
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ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
106
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CBSE
2005
Springer
15 years 5 months ago
2005
Springer
We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...
86
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ICCAD
1997
IEEE
15 years 4 months ago
1997
IEEE
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...