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    » A Framework for Scheduler Synthesis
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    DATE
    1998
    IEEE
    68views Hardware» more  DATE 1998»
    Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems
    15 years 4 months ago
    Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems
    Download  www.ida.liu.se
    We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of severa...
    Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
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    ASPDAC
    1995
    ACM
    77views Hardware» more  ASPDAC 1995»
    A scheduling algorithm for synthesis of bus-partitioned architectures
    15 years 3 months ago
    A scheduling algorithm for synthesis of bus-partitioned architectures
    Download  www.cs.york.ac.uk
    - Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
    Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi T...
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    ECRTS
    2003
    IEEE
    71views Embedded Systems» more  ECRTS 2003»
    Synthesis of Safe, QoS Extendible, Application Specific Schedulers for Heterogeneous Real-Time Systems
    15 years 5 months ago
    Synthesis of Safe, QoS Extendible, Application Specific Schedulers for Heterogeneous Real-Time Systems
    Download  www.soi.city.ac.uk
    Christos Kloukinas, Sergio Yovine
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    ISCAS
    2003
    IEEE
    103views Hardware» more  ISCAS 2003»
    An ILP-based scheduling scheme for energy efficient high performance datapath synthesis
    15 years 5 months ago
    An ILP-based scheduling scheme for energy efficient high performance datapath synthesis
    Download  www.cse.unt.edu
    Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
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    ITC
    2000
    IEEE
    62views Hardware» more  ITC 2000»
    Power conscious test synthesis and scheduling for BIST RTL data paths
    15 years 3 months ago
    Power conscious test synthesis and scheduling for BIST RTL data paths
    Download  dit.upc.es
    Nicola Nicolici, Bashir M. Al-Hashimi
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