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» A Framework for Scheduler Synthesis
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ISLPED
1997
ACM
124views Hardware» more  ISLPED 1997»
15 years 4 months ago
Low power high level synthesis by increasing data correlation
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
Dongwan Shin, Kiyoung Choi
ICCAD
1992
IEEE
93views Hardware» more  ICCAD 1992»
15 years 3 months ago
Timing analysis in high-level synthesis
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
Andreas Kuehlmann, Reinaldo A. Bergamaschi
CORR
2008
Springer
118views Education» more  CORR 2008»
14 years 12 months ago
A Logic Programming Framework for Combinational Circuit Synthesis
Abstract. Logic Programming languages and combinational circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts ...
Paul Tarau, Brenda Luderman
ICFP
2008
ACM
15 years 11 months ago
A scheduling framework for general-purpose parallel languages
The trend in microprocessor design toward multicore and manycore processors means that future performance gains in software will largely come from harnessing parallelism. To reali...
Matthew Fluet, Mike Rainey, John H. Reppy
DELTA
2006
IEEE
15 years 5 months ago
Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication
We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replicati...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...