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» A Framework for Scheduler Synthesis
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ICCAD
1995
IEEE
114views Hardware» more  ICCAD 1995»
15 years 5 months ago
Sequential synthesis using S1S
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
Adnan Aziz, Felice Balarin, Robert K. Brayton, Alb...
EUROMICRO
1999
IEEE
15 years 6 months ago
Design Space Exploration in System Level Synthesis under Memory Constraints
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constra...
Radoslaw Szymanek, Krzysztof Kuchcinski
ISSS
1997
IEEE
109views Hardware» more  ISSS 1997»
15 years 6 months ago
Reducing the Complexity of ILP Formulations for Synthesis
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases. There exists some tools that give an o...
Anne Mignotte, Olivier Peyran
MEMOCODE
2007
IEEE
15 years 8 months ago
Scheduling as Rule Composition
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
Nirav Dave, Arvind, Michael Pellauer
DATE
2000
IEEE
119views Hardware» more  DATE 2000»
15 years 6 months ago
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis
We present an approach to bus access optimization and schedulability analysis for the synthesis of hard real-time distributed embedded systems. The communication model is based on...
Paul Pop, Petru Eles, Zebo Peng