1420 search results - page 43 / 284 » A Framework for Scheduler Synthesis |
125
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DATE
2000
IEEE
15 years 6 months ago
2000
IEEE
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
IFIP
1992
Springer
15 years 6 months ago
1992
Springer
In microarchitecure synthesis, early algorithms considered only a single implementation technique for IF -statements. Focus was on scheduling and on maximum hardware sharing. In t...
101
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CODES
1997
IEEE
15 years 6 months ago
1997
IEEE
– Retargetability of embedded system descriptions not only enables better exploration of the design space and evaluation of cost/performance tradeoffs but also enhances design ma...
SECON
2010
IEEE
14 years 12 months ago
2010
IEEE
Abstract--Recurrent applications that mostly run in the background are a significant source of power consumption on batterylimited mobile phones. We highlight the pitfalls of sched...
128
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VLSID
2006
IEEE
16 years 2 months ago
2006
IEEE
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...