1420 search results - page 44 / 284 » A Framework for Scheduler Synthesis |
115
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VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
122
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CODES
2006
IEEE
15 years 5 months ago
2006
IEEE
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
131
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ICCAD
1995
IEEE
15 years 5 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
129
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GLVLSI
2000
IEEE
15 years 6 months ago
2000
IEEE
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
125
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FSEN
2009
Springer
15 years 5 months ago
2009
Springer
This note aims at providing a concise and precise Travellers Guide, Phrase Book or Reference Manual to the timed automata modeling formalism introduced by Alur and Dill [7, 8]. The...