1420 search results - page 5 / 284 » A Framework for Scheduler Synthesis |
VLSID
1994
IEEE
15 years 1 months ago
1994
IEEE
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
75
Voted
CEC
2008
IEEE
15 years 4 months ago
2008
IEEE
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
108
click to vote
DAC
1998
ACM
15 years 1 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
89
Voted
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synch...
ICCAD
1992
IEEE
15 years 1 months ago
1992
IEEE
High-level synthesis (HLS) requires more designer interaction to better meet the needs of experienced designers. However, attempts to create a highly interactive synthesis process...