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» A Framework for Scheduler Synthesis
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DT
2010
99views more  DT 2010»
14 years 9 months ago
CEDA Currents
specified at levels of abstraction higher than the Register Transfer Level (RTL) in hardware description. The essential feature of a behavioral description is that, the designer on...
ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Using speculative computation and parallelizing techniques to improve scheduling of control based designs
Recent research results have seen the application of parallelizing techniques to high-level synthesis. In particular, the effect of speculative code transformations on mixed contr...
Roberto Cordone, Fabrizio Ferrandi, Marco D. Santa...
VC
2010
165views more  VC 2010»
14 years 7 months ago
Generating animation from natural language texts and semantic analysis for motion search and scheduling
This paper presents an animation system that generates an animation from natural language texts such as movie scripts or stories. It also proposes a framework for a motion database...
Masaki Oshita
DSD
2002
IEEE
88views Hardware» more  DSD 2002»
15 years 2 months ago
The Synthesis of a Hardware Scheduler for Non-Manifest Loops
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...
Omar Mansour, Egbert Molenkamp, Thijs Krol
EUROMICRO
1998
IEEE
15 years 1 months ago
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...