24 search results - page 1 / 5 » A Fully Asynchronous Superscalar Architecture |
71
Voted
IEEEPACT
1999
IEEE
15 years 1 months ago
1999
IEEE
An asynchronous superscalar architecture is presented based on a novel architectural feature called instruction compounding. This enables efficient dynamic scheduling and forwardi...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
89
Voted
CHES
2006
Springer
15 years 1 months ago
2006
Springer
Abstract. We propose a superscalar coprocessor for high-speed curvebased cryptography. It accelerates scalar multiplication by exploiting instruction-level parallelism (ILP) dynami...
ICCD
2003
IEEE
15 years 6 months ago
2003
IEEE
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...
103
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HPCA
2006
IEEE
15 years 9 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...