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» A Fully Asynchronous Superscalar Architecture
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ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
15 years 7 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
FPL
2010
Springer
134views Hardware» more  FPL 2010»
14 years 11 months ago
GPU Versus FPGA for High Productivity Computing
Heterogeneous or co-processor architectures are becoming an important component of high productivity computing systems (HPCS). In this work the performance of a GPU based HPCS is c...
David Huw Jones, Adam Powell, Christos-Savvas Boug...
ACHI
2009
IEEE
15 years 4 months ago
SCRABBLE.GZ: A Web-Based Collaborative Game to Promote the Galician Language
We present in this paper a web-based version of a Scrabble game, describing its architecture and some implementation details. This architecture makes possible a high degree of int...
Guillermo de Bernardo, Ana Cerdeira-Pena, Oscar Pe...
ICRA
2003
IEEE
104views Robotics» more  ICRA 2003»
15 years 6 months ago
Enhancing the reactive capabilities of integrated planning and control with cooperative extended kohonen maps
— Despite the many significant advances made in robot motion research, few works have focused on the tight integration of high-level deliberative planning with reactive control ...
Kian Hsiang Low, Wee Kheng Leow, Marcelo H. Ang Jr...
ASPLOS
2012
ACM
13 years 9 months ago
Providing safe, user space access to fast, solid state disks
Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state...
Adrian M. Caulfield, Todor I. Mollov, Louis Alex E...