189 search results - page 3 / 38 » A Functional DBPL Revealing High Level Optimizations |
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
92
Voted
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
ISQED
2007
IEEE
15 years 3 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
83
Voted
IWPC
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper presents a framework for software architecture recovery and restructuring. The user specifies a high level abstraction view of the system using a structured pattern la...
88
Voted
TPCTC
2010
Springer
14 years 4 months ago
2010
Springer
Abstract. Event Processing (EP) systems are being progressively used in business critical applications in domains such as algorithmic trading, supply chain management, production m...