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MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
15 years 3 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
100
Voted
ISHPC
1999
Springer
15 years 1 months ago
Integrity and Performance in Network Attached Storage
Computer security is of growing importance in the increasingly networked computing environment.This work examines the issue of high-performance network security, specifically int...
Howard Gobioff, David Nagle, Garth A. Gibson
CF
2009
ACM
15 years 4 months ago
Strategies for dynamic memory allocation in hybrid architectures
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
Peter Bertels, Wim Heirman, Dirk Stroobandt
PLDI
2011
ACM
14 years 9 days ago
Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors
MATLAB is an array language, initially popular for rapid prototyping, but is now being increasingly used to develop production code for numerical and scientific applications. Typ...
Ashwin Prasad, Jayvant Anantpur, R. Govindarajan
130
Voted
IADIS
2009
14 years 7 months ago
A strategy for cost efficient distributed data storage for in-memory OLAP
With the availability of inexpensive blade servers featuring 32 GB or more of main memory, memory-based engines such as the SAP NetWeaver Business Warehouse Accelerator are coming...
Olga Mordvinova, Oleksandr Shepil, Thomas Ludwig 0...