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111
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DAC
2004
ACM
16 years 1 months ago
ORACLE: optimization with recourse of analog circuits including layout extraction
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
DAC
2005
ACM
16 years 1 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
DAC
2006
ACM
16 years 1 months ago
Timing-based delay test for screening small delay defects
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
111
Voted
DAC
2006
ACM
16 years 1 months ago
HybDTM: a coordinated hardware-software approach for dynamic thermal management
With ever-increasing power density and cooling costs in modern high-performance systems, dynamic thermal management (DTM) has emerged as an effective technique for guaranteeing th...
Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K....
136
Voted
ICML
1999
IEEE
16 years 1 months ago
Least-Squares Temporal Difference Learning
Excerpted from: Boyan, Justin. Learning Evaluation Functions for Global Optimization. Ph.D. thesis, Carnegie Mellon University, August 1998. (Available as Technical Report CMU-CS-...
Justin A. Boyan
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