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» A General Semantics for Evaluation Logic
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FPL
2006
Springer
223views Hardware» more  FPL 2006»
15 years 1 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
UAI
2008
14 years 11 months ago
Improving the Accuracy and Efficiency of MAP Inference for Markov Logic
In this work we present Cutting Plane Inference (CPI), a Maximum A Posteriori (MAP) inference method for Statistical Relational Learning. Framed in terms of Markov Logic and inspi...
Sebastian Riedel
APLAS
2006
ACM
15 years 4 months ago
Relational Reasoning for Recursive Types and References
We present a local relational reasoning method for reasoning about contextual equivalence of expressions in a λ-calculus with recursive types and general references. Our developme...
Nina Bohr, Lars Birkedal
BIRTHDAY
2004
Springer
15 years 3 months ago
Composing Hidden Information Modules over Inclusive Institutions
: This paper studies the composition of modules that can hide information, over a very general class of logical systems called inclusive institutions. Two semantics are given for c...
Joseph A. Goguen, Grigore Rosu
ICLP
2009
Springer
15 years 10 months ago
Modular Nonmonotonic Logic Programming Revisited
Recently, enabling modularity aspects in Answer Set Programming (ASP) has gained increasing interest to ease the composition of program parts to an overall program. In this paper, ...
Minh Dao-Tran, Thomas Eiter, Michael Fink, Thomas ...