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» A Genetic Testing Framework for Digital Integrated Circuits
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78
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ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
15 years 1 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
ET
2007
69views more  ET 2007»
14 years 9 months ago
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST
Abstract In order to perform an on-chip test for characterizing both static and transmission parameters of embedded analog-to-digital converters (ADCs), this paper presents an osci...
Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh ...
DATE
2003
IEEE
152views Hardware» more  DATE 2003»
15 years 2 months ago
Synthesis of CMOS Analog Cells Using AMIGO
In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A fram...
Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud...
SIGSOFT
2003
ACM
15 years 10 months ago
Regression testing of GUIs
Although graphical user interfaces (GUIs) constitute a large part of the software being developed today and are typically created using rapid prototyping, there are no effective r...
Atif M. Memon, Mary Lou Soffa
71
Voted
DAC
2006
ACM
15 years 10 months ago
A new LP based incremental timing driven placement for high performance designs
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Tao Luo, David Newmark, David Z. Pan