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» A Genetic Testing Framework for Digital Integrated Circuits
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DATE
2009
IEEE
88views Hardware» more  DATE 2009»
15 years 1 months ago
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
Xiao Liu, Qiang Xu
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
15 years 1 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
TCAD
2002
110views more  TCAD 2002»
14 years 9 months ago
A constructive genetic algorithm for gate matrix layout problems
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
Alexandre César Muniz de Oliveira, Luiz Ant...
GECCO
2006
Springer
215views Optimization» more  GECCO 2006»
15 years 1 months ago
A multi-chromosome approach to standard and embedded cartesian genetic programming
Embedded Cartesian Genetic Programming (ECGP) is an extension of Cartesian Genetic Programming (CGP) that can automatically acquire, evolve and re-use partial solutions in the for...
James Alfred Walker, Julian Francis Miller, Rachel...
TIFS
2008
120views more  TIFS 2008»
14 years 9 months ago
Determining Image Origin and Integrity Using Sensor Noise
In this paper, we provide a unified framework for identifying the source digital camera from its images and for revealing digitally altered images using photo-response nonuniformit...
Mo Chen, Jessica J. Fridrich, Miroslav Goljan, Jan...