136 search results - page 6 / 28 » A Graph Reduction Approach to Symbolic Circuit Analysis |
DAC
2005
ACM
14 years 11 months ago
2005
ACM
On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem ext...
129
click to vote
TIM
2010
14 years 4 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
– Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the...
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
— As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessi...
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...