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ERSA
2009
14 years 7 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
MICRO
2006
IEEE
15 years 4 months ago
2006
IEEE
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
ISCA
2006
IEEE
15 years 4 months ago
2006
IEEE
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
NIPS
2000
14 years 11 months ago
2000
We analyze the bit error probability of multiuser demodulators for directsequence binary phase-shift-keying (DS/BPSK) CDMA channel with additive gaussian noise. The problem of mul...
SAT
2010
Springer
14 years 8 months ago
2010
Springer
Previous work has shown that circuit representations can be exploited in QBF solvers to obtain useful performance improvements. In this paper we examine some additional techniques ...