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ITC
2002
IEEE
15 years 3 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ISLPED
2010
ACM
14 years 8 months ago
2010
ACM
The shift towards multicore processors and the well-known drawbacks imposed by lock-based synchronization have forced researchers to devise new alternatives for building concurren...
ISCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Inclusive last-level caches (LLCs) waste precious silicon estate due to cross-level replication of cache blocks. As the industry moves toward cache hierarchies with larger inner l...
62
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IPCV
2008
14 years 11 months ago
2008
This paper presents a new feature point detector that is accurate, efficient and fast. A detailed qualitative evaluation of the proposed feature point detector for grayscale images...
116
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ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...