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MICRO
2007
IEEE
108views Hardware» more  MICRO 2007»
15 years 4 months ago
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...
ASPDAC
2005
ACM
120views Hardware» more  ASPDAC 2005»
15 years 9 days ago
STACCATO: disjoint support decompositions from BDDs through symbolic kernels
Abstract— A disjoint support decomposition (DSD) is a representation of a Boolean function F obtained by composing two or more simpler component functions such that the component...
Stephen Plaza, Valeria Bertacco
APCCAS
2006
IEEE
252views Hardware» more  APCCAS 2006»
15 years 9 days ago
A Display Order Oriented Scalable Video Decoder
As network technologies advance, Scalable Video Coding (SVC) has become increasingly popular due to its universal multimedia access capability and competitive compression performan...
Jia-Bin Huang, Yu-Kun Lin, Tian-Sheuan Chang
ARC
2010
Springer
126views Hardware» more  ARC 2010»
14 years 8 months ago
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challe...
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyse...
CODES
2005
IEEE
15 years 4 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung