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ICS
2009
Tsinghua U.
15 years 2 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
ISCA
2010
IEEE
284views Hardware» more  ISCA 2010»
15 years 2 months ago
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address
Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and...
Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
15 years 1 months ago
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such netw...
Leonidas I. Kontothanassis, Galen C. Hunt, Robert ...
PVG
2003
IEEE
138views Visualization» more  PVG 2003»
15 years 2 months ago
Sort-First, Distributed Memory Parallel Visualization and Rendering
While commodity computing and graphics hardware has increased in capacity and dropped in cost, it is still quite difficult to make effective use of such systems for general-purpos...
E. Wes Bethel, Greg Humphreys, Brian E. Paul, J. D...
CASES
2003
ACM
15 years 2 months ago
Clustered calculation of worst-case execution times
Knowing the Worst-Case Execution Time (WCET) of a program is necessary when designing and verifying real-time systems. A correct WCET analysis method must take into account the po...
Andreas Ermedahl, Friedhelm Stappert, Jakob Engblo...