193 search results - page 2 / 39 » A High Level Power Model for the Nostrum NoC |
MASCOTS
2007
2007
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
13 years 7 months ago
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
ISCA
2008
IEEE
14 years 21 days ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
DSD
2008
IEEE
14 years 22 days ago
2008
IEEE
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...