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80
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ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
15 years 4 months ago
Reconfigurable Fast Memory Management System Design for Application Specific Processors
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...
S. Kagan Agun, J. Morris Chang
IPPS
2006
IEEE
15 years 5 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
103
Voted
ARC
2010
Springer
183views Hardware» more  ARC 2010»
14 years 11 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
118
Voted
DOA
2001
97views more  DOA 2001»
15 years 1 months ago
Transparent Dynamic Reconfiguration for CORBA
Distributed systems with high availability requirements have to support some form of dynamic reconfiguration. This means that they must provide the ability to be maintained or upg...
João Paulo A. Almeida, Maarten Wegdam, Mart...
CODES
2009
IEEE
15 years 3 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...