3037 search results - page 78 / 608 » A High Performance Application Representation for Reconfigur... |
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ISSS
2000
IEEE
15 years 4 months ago
2000
IEEE
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
COMPGEOM
2001
ACM
15 years 3 months ago
2001
ACM
This paper addresses the problem of lossy compression of arrangements. Given an arrangement of n lines in the plane, we show how to construct another arrangement consisting of man...
106
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TC
2011
14 years 6 months ago
2011
—CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and ...
110
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ISPASS
2003
IEEE
15 years 5 months ago
2003
IEEE
Emerging application domains such as interactive vision, animation, and multimedia collaboration display dynamic scalable parallelism, and high computational requirements, making ...
ARC
2007
Springer
15 years 3 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...