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TVLSI
2010
14 years 6 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
HPCN
1998
Springer
15 years 4 months ago
Application Execution Steering using On-the-Fly Performance Prediction
The execution of an application on a high performance system requires parameters concerning the problem in hand, and those that determine the system mapping, to be specified by a ...
Darren J. Kerbyson, Efstathios Papaefstathiou, Gra...
HPCA
2003
IEEE
16 years 7 days ago
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
Russ Joseph, David Brooks, Margaret Martonosi
PVLDB
2010
204views more  PVLDB 2010»
14 years 10 months ago
Cheetah: A High Performance, Custom Data Warehouse on Top of MapReduce
Large-scale data analysis has become increasingly important for many enterprises. Recently, a new distributed computing paradigm, called MapReduce, and its open source implementat...
Songting Chen
CODES
2006
IEEE
15 years 3 months ago
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel suppo...
Hayden Kwok-Hay So, Artem Tkachenko, Robert W. Bro...