30 search results - page 6 / 6 » A High Performance Hardware Architecture for One Bit Transfo... |
DAC
2009
ACM
13 years 10 months ago
2009
ACM
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
BMCBI
2010
13 years 6 months ago
2010
Background: Solving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve...
CEE
2007
13 years 6 months ago
2007
It is a challenge to implement large word length public-key algorithms on embedded systems. Examples are smartcards, RF-ID tags and mobile terminals. This paper presents a HW/SW c...
MICRO
1997
IEEE
13 years 10 months ago
1997
IEEE
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
RTAS
2010
IEEE
13 years 4 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...