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» A High Performance Kernel-Less Operating System Architecture
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WCRE
2002
IEEE
15 years 8 months ago
Register Liveness Analysis for Optimizing Dynamic Binary Translation
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
Mark Probst, Andreas Krall, Bernhard Scholz
106
Voted
IMS
2000
123views Hardware» more  IMS 2000»
15 years 7 months ago
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of...
David Judd, Katherine A. Yelick, Christoforos E. K...
151
Voted
IEEEHPCS
2010
14 years 10 months ago
XPSoC: A reconfigurable solution for multimedia contents protection
Network Multimedia data also need to be encrypted to protect private content and access control. Considering performance constraints and embedded system issues, many hardware solu...
Linfeng Ye, Jean-Philippe Diguet, Guy Gogniat
IPPS
1999
IEEE
15 years 8 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin
130
Voted
DAC
2002
ACM
16 years 4 months ago
Analysis of power consumption on switch fabrics in network routers
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
Terry Tao Ye, Giovanni De Micheli, Luca Benini