3104 search results - page 371 / 621 » A High Performance Kernel-Less Operating System Architecture |
128
click to vote
ISLPED
2004
ACM
15 years 9 months ago
2004
ACM
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
135
click to vote
FPL
2009
Springer
15 years 8 months ago
2009
Springer
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
122
Voted
DAC
2000
ACM
16 years 4 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
112
Voted
WMPI
2004
ACM
15 years 9 months ago
2004
ACM
The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. ...
155
click to vote
RTAS
2010
IEEE
15 years 1 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...