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» A High Performance Kernel-Less Operating System Architecture
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MICRO
2008
IEEE
109views Hardware» more  MICRO 2008»
15 years 4 months ago
Dependence-aware transactional memory for increased concurrency
—Transactional memory (TM) is a promising paradigm for helping programmers take advantage of emerging multicore platforms. Though they perform well under low contention, hardware...
Hany E. Ramadan, Christopher J. Rossbach, Emmett W...
SIGMOD
2010
ACM
259views Database» more  SIGMOD 2010»
15 years 2 months ago
PODS: a new model and processing algorithms for uncertain data streams
Uncertain data streams, where data is incomplete, imprecise, and even misleading, have been observed in many environments. Feeding such data streams to existing stream systems pro...
Thanh T. L. Tran, Liping Peng, Boduo Li, Yanlei Di...
ISPASS
2007
IEEE
15 years 4 months ago
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinric...
DFT
2005
IEEE
109views VLSI» more  DFT 2005»
15 years 3 months ago
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
In this paper, we propose a system-level error tolerance scheme for systems where a linear transform is combined with quantization. These are key components in multimedia compress...
In Suk Chong, Antonio Ortega
LCTRTS
2007
Springer
15 years 4 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...