The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
A wide spectrum of e-commerce (B2B/B2C), banking, financial trading and other business applications require the exchange of data to be highly secure. The Secure Sockets Layer (SSL...
Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. ...
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...