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» A High-speed Architecture for Building Hybrid Minds

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RTAS
1997
IEEE

176views Embedded Systems» more RTAS 1997»

Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches

15 years 2 months ago

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ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...

Sung-Whan Moon, Kang G. Shin, Jennifer Rexford

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GLVLSI
2005
IEEE

132views VLSI» more GLVLSI 2005»

FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks

15 years 4 months ago

Download hvg.ece.concordia.ca

In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...

Abdallah Merhebi, Otmane Aït Mohamed

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ICAART
2011
INSTICC

250views Intelligent Agents» more ICAART 2011»

A High-speed Architecture for Building Hybrid Minds

14 years 2 months ago

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