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» A High-speed Architecture for Building Hybrid Minds
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RTAS
1997
IEEE
15 years 1 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
81
Voted
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
15 years 3 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
ICAART
2011
INSTICC
14 years 1 months ago
A High-speed Architecture for Building Hybrid Minds
Oisín Mac Fhearaí, Mark Humphrys, Ra...