145 search results - page 13 / 29 » A Higher-Level Language for Hardware Synthesis |
ENTCS
2010
14 years 9 months ago
2010
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
COMPSEC
2008
14 years 9 months ago
2008
While general-purpose processor based systems are built to enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reco...
FDL
2007
IEEE
15 years 4 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
ISSS
2002
IEEE
15 years 2 months ago
2002
IEEE
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
MSE
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short co...