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» A Higher-Level Language for Hardware Synthesis
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DFT
2007
IEEE
123views VLSI» more  DFT 2007»
15 years 4 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
80
Voted
CODES
1999
IEEE
15 years 1 months ago
How standards will enable hardware/software co-design
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
FPL
2007
Springer
190views Hardware» more  FPL 2007»
15 years 3 months ago
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems
Today’s heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of thes...
Andreas Herrholz, Frank Oppenheimer, Philipp A. Ha...
EMSOFT
2004
Springer
15 years 3 months ago
Loose synchronization of event-triggered networks for distribution of synchronous programs
Dataflow synchronous languages have attracted considerable interest in domains such as real-time control and hardware design. The potential benefits are promising: Discrete-time...
Jan Romberg, Andreas Bauer 0002
94
Voted
ECBS
1999
IEEE
171views Hardware» more  ECBS 1999»
15 years 1 months ago
Metamodeling - Rapid Design and Evolution of Domain-Specific Modeling Environments
Model integrated computing (MIC) is gaining increased attention as an effective and efficient method for developing, maintaining, and evolving large-scale, domain-specific softwar...
Greg Nordstrom, Janos Sztipanovits, Gabor Karsai, ...